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MN103E010HRA, MN103E040HYB
Type Instruction Cache Data Cashe SRAM Used by Both Instructions and Data Package Minimum Instruction Execution Time Interrupts Timer Counter
MN103E010HRA 16 K-byte (4-way, set-associative) 16 K-byte (4-way, set-associative) 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free MN103E040HYB
7.5 ns (at 1.8 V tolerance = 5%, 133 MHz) * XIRQ x 8 * NMI * Timer x 14 * DMAC x 4 * WDT * A/D * SIO x 6 * I2C x 2 * IrDA * Softmodem * Realtime clock * Asynchronous bus error 8-bit timer x 4 (all down counters) Cascade connection possible (usable as a 16/24/32-bit timer) Timer output possible (Duty = 1:1) Internal clock source or external clock source selectable Selectable as a serial interface clock 16-bit timer x 7 (down counters) Cascade connection possible (usable as a 32-bit timer) Timer output possible (Duty = 1:1) Internal clock source or external clock source selectable Partially selectable as a serial interface clock 16-bit timer x 1 (up counter) Internal clock source or external clock source selectable Input capture function (rising edge, falling edges, or both selectable) PWM generating function (compare/capture register x 2 contained) Watchdog timer x 1
DMA Contoroller
Number of channels: 4 Transfer unit: 1/2/4/16 byte Maximum number of bytes transferred: 1Mbyte Start factor: External request, interrupt, software Transfer mode: 2-bus cycle transfer Transfer mode: Batch transfer, intermittent transfer Addressing mode: Source/destination each fixed, increment/decrement specification possible Increment/decrement automatically executed according to the transfer unit UART/synchronous (co-used) x 2-ch. UART (with CTS control) x 1-ch.
Serial Interface I/O Pins I/O
34
* Common use : 33
FPU (floating point unit)
* Data types complying with the IEEE754 standard supported * Round to the nearest mode complying with the IEEE754 standard supported * 32 single-precision floating point operation registers (FS0-FS31) These can also be referenced as 16 double-precision floating point operation registers (FD0-FD30) * Floating point operation exceptions (5 types) and floating point unload instruction exceptions complying with the IEEE754 standard supported 32-entry full-associative TLB loaded (instructions/data separated from each other) Address conversion by paging (page size: 1 K-byte. 4 K-byte, 128 K-byte, 4 M-byte variable) Concurrent access from three types of master devices to four types of slave devices possible
Memory Management Function On-chip Bus Controller
1
MAF00006EEM
MN103E010HRA, MN103E040HYB
System Bus Interface Memory Bus Interface Soft Modem Interface
External memory space allocation to 8 banks possible The external interface can use the built-in memory, RAM, ROM, SDRAM interfaces SDRAM directly connected interface contained * Interface with an external AFE (analog front end) * Output data parallel-serial conversion, input data serial-parallel conversion * Send/receive FIFO contained (16-bit width, 16 steps) * NCU control via the parallel IO port * Clock/calendar function * Interrupt: periodic, alarm, update ended * BCD/binary accommodated * Leap year automatic correcting function * 24-hout/12-hour selectable * Daylight saving time mode accommodated * 10-bit charge re-distribution mode (error: 4LSB) * Number of channels: 8-channel * IrDA 1.0 SIR (-115.2 Kb/s, half-duplex) * IrDA 1.1 MIR (0.576, 1.152 Mb/s, half-duplex) * IrDA 1.1 FIR (4.0 Mbp/s, half-duplex) * UART (-1.5 Mbp/s, full-duplex) * 48 MHz clock input (baud rate generating function contained) 2 ports Master-slave interface (multi-master supported) 3.3 V interface (open drain output)
Real-time Clock
A/D Converter IrDA Interface
I2C Interface
Electrical Characteristics
Supply current
Parameter Operating supply current Supply current at stopping
Symbol
Condition
VDD18 = 1.8 V ; VDD33, PVDD, AVDD, RVDD = 3.3 V
Limit min
- -
typ
- -
max
460
Unit
IDD18A fOSC = 33.33 MHz (core 133 MHz) ; FRQS[1:0] = 0.0 ; Output open VDD18 = 1.89 V ; VDD33, PVDD, AVDD, RVDD = 3.465 V IDD18D fOSC = Stop ; FRQS[1:0] = 0.0 ; Output open ; Tj = 70C
mA
50
mA
(Ta = -20C to +70C)
A/D conversion performance
Parameter Resolution A/D conversion relative error
A/D conversion differential non-linear error
Symbol
Condition
Limit min
- - - 2.6
typ
- - - -
max
10 4 4 -
Unit
Bit LSB LSB s
VREFH = 3.3 V Conversion reference clock = 4.166 MHz
A/D conversion time
(Ta = -20C to +70C, AVDD = 3.3 V 0.165 V, AVSS = 0 V)
See the next page for pin assignment and support tool.
MAF00006EEM
2
Pin Assignment
Perspective
XSWE1 XSCS6 XSCS2 XSCS1 SD29 SD27 VDD18 SD21 SD19 SD14 VDD18 SD6 ND XSWE3 SD31 XSCS7 SD30 XSAS SD23 SD22 SD17 SD16 SD9 SD8 SD3
SD1 CLK48 PIO1[3] PIO1[1] PIO1[0] ND SD4 PIO5[1] PIO5[2] PIO1[4] PIO1[2] AN3 AN7 VREFH
21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02
ND
RCLKI XSCS3 XSWE0 XSWE2 XSCS0 XSCS4 SD28 SD25 SD24 SD18 VDD33 SD15 SD11 SD10 VDD33 PIO0[7] PIO5[0] AN1 RCLKO PIO2[0] PWROK RVDD PIO2[4] PIO2[2] TCPOUT PIO2[3] XSDK ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND SD26 SD20 SD13 SD12 SD7 ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND VSS VSS VSS VSS VSS ND ND ND ND ND ND ND ND VSS VSS VSS VSS VSS ND ND ND ND ND ND ND ND VSS VSS VSS VSS VSS ND ND ND ND SD2 ND ND ND ND VSS VSS VSS VSS VSS ND ND ND ND SD0 ND ND ND ND VSS VSS VSS VSS VSS ND ND ND ND SD5 PIO0[1] ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND
AN5 PIO0[5] AVSS AN6 AN0 AN2
PIO0[3] XIRQ7 AN4
PVDD SSZ0 XSBG VDD33 PVSS SA4 SA2 XSCS5
ND XIRQ4 SBT2 PIO0[4] AVDD ND ND ND SBO0 XIRQ5 XNMI XIRQ2 SBO1 XIRQ0 PIO0[6] PIO0[2] VDD33 XRESET PIO0[0] XIRQ6
OSCI SA10 SA5 VDD33 OSCO SA17 SA11 SA0 SYSCLK SA18 SA12 XSRE PIO2[1] SRXW SSZ1 VDD33 XSBR VDD18 SA9 SA1 SA6 SA3 SA14 SA7 SA8
ND TRCST VDD33 XIRQ3 VDD18 ND ND ND ND ND ND ND SBI1 SBI2 SBO2 XIRQ1 PIO3[2] PIO3[3] XRSTOUT VDD18 PIO3[0] PIO3[1] SBT0 SBT1 TRST PIO4[0] PIO4[2] SBI0 MOD ND ND ND PIO4[1] PIO3[4] TCK TRCD1 PIO4[3] TDI TRCD5 TMS TDO
SA13 SA15 SA22 ND ND ND
SA16 SA19 SA21 VDD18 SA23 VDD33 SA27 SA26 SA24
VDD33 VDD18 VDD33 VDD33 VDD33 VDD33 VDD18 TRCD2 TRCD7 ND
SA29 SA31 SA25 SA20 SA28 MA4 MA1 MA7 MA13 MA11 MA12 XMBE0 MD9 MD4 MD12 MD1 MD15 TRCD4 TRCD0 EXTRG TRCCLK SA30 MA3 MA5 MA0 MA8 MA14 XMCS1 SDCKE XMWE XMCAS MD6 MD10 MD11 MD2 MD14 TRCD3 TRCD6 ND NP MA2 MA6 MA10 MA9 XMCS0 XMRAS SDCLK XMBE1 MDK MD7 MD8 MD5 SDCKI MD3 MD13 MD0
01
A
B
C
D
E
F
G
H
J
K
LMN
P
R
T
U
V W Y AA
FLGA424-C-1717
*Lead-free
* ND has an electrode (pin) but N.C. is not guaranteed. Please design so as not to cause short circuit with other wiring on the user board. * The NDs on the four corners are the lands intended for reinforcement. You are required to connect them to the PCB. * NP (No pin.) has no electrode.
3
MAF00006EEM
MN103E010HRA, MN103E040HYB
Pin Assignment(Continue)
Perspective
TRCD6 TRCD1 TRCD3 EXTRG
TDO TCK
TRST PIO4[2] PIO3[2] MOD
SBI0
SBO1 SBI1
SBT1
SBT2
XRST XIRQ1 XIRQ4 XIRQ5 PIO0[0] PIO0[4] AVDD OUT AN6 AN7 AN5 AN2 AN3
AN4 AN1 AN0
AVSS VREFH PIO1[2] PIO5[0] PIO1[1] PIO5[2]
20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
PIO4[0] PIO3[0] PIO3[3] SBO0 TDI VSS VSS VSS VD33 VD18 TMS VSS
SBI2 XIRQ0 XIRQ2 XNMI XIRQ7 PIO0[2] PIO0[6] SBT0 SBO2 XRESET XIRQ3 XIRQ6 PIO0[1] PIO0[5] VSS PIO0[3] VSS PIO0[7]
TRCD7 TRCD4 TRCD0 MD0 MD13 MD3 sdcki MD5 MD8 MD7 TRCD2 TRCD5 TRC CLK TRCST
PIO4[1] PIO3[1] PIO3[4] PIO4[3] VDD18 VDD33
VSS VDD18 VDD33
PIO1[0] PIO1[3] PIO5[1] CLK48 VSS SD2 VDD33 PIO1[4] SD1 SD5 SD8 SD3 SD6 SD9 SD12 SD15 SD17 SD18 SD20 SD24 SD27 SD30 SD0 SD4 SD7 SD10 SD13 SD16 SD19 SD22 SD26 SD28 SD31
MD14 MD15 MD2 MD1
MD11 MD12 MD10 MD6
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS
MD4 VDD33 MD9 VSS
VDD18 SD11 VDD33 SD14 VSS SD23
MDK XMCAS XMBE0 VDD33 XMBEl XMWE MA12 VSS
VDD18 SD21 VSS SD25
SDCLK SDCKE MA11 VDD18 XMRAS XMCE1 MA13 VDD33 XMCS0 MA14 MA9 MA10 MA6 MA2 SA30 MA8 MA0 MA5 MA3 SA29 MA7 VDD33 MA1 MA4 SA31 SA28 SA27 VSS VSS SA26 SA25 SA24 VSS SA23 SA21 SA20
VDD33 SD29 XSCS2 XSAS VSS SA22 VDD18 VDD33 VSS SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA9 SA8 SA7 VDD33 SA10 SA6 SA5 SA0 SA1 SA2 SA4 XSBR XSRE VDD18 VDD33 XSBG PIO2[4] PIO2[3] PIO2[0] SSZ0 SA3 SRXW PIO2[2] PIO2[1] SSZ1 XSDK SYS CLK VSS VSS
XSCS3 XSCS0 XSCS1 XSCS6 XSCS4 XSCS5
VSS XSWE3 XSWE0 XSCS7 RCLKI TCP PWROK XSWE2 XSWE1 RCLKO OUT OSCO OSCI PVSS PVDD RVDD
A
B
C
D
E
F
G
H
J
K
L
M
*Lead-free
N
P
R
T
U
V
W
Y
BGA292-P-2727
Support Tool
ROM Emulator On-board Development Tools
PARTNER-ETII (KMC product) PX-ODB103E-J (On-board debug unit) PX-ODB-AMT-20 (Trace unit) PARTNER-J (KMC product)
MAF00006EEM
4
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